A guide to overclocking your RAM timings is as follows: start with Trfc,
then Trc and then Trrd, Twr, Twtr, and Trtw values. I wouldn't go lower
than 2 for Trrd and Twr if you ram can handle it.
Here's a chart about the different RAM timings. I will cite sources for
info wherever I can.
Timing
Expanded description
Detailed description
tCL
CAS# Latency
CAS is Column Address Strobe or Column
Address Select. CAS controls the amount of time (in cycles (2,
2.5,& 3) between receiving a command and acting on that command.
Since CAS primarily controls the location of HEX addresses, or
memory columns, within the memory matrix, this is the most
important timing to set as low as your system will stably accept
it. There are both rows and columns inside a memory matrix. When
the request is first electronically set on the memory pins, the
first triggered response is tRAS (Active to Precharge Delay).
Data requested electronically is precharge, and the memory
actually going to initiate RAS is activation. Once tRAS is
active, RAS, or Row Address Strobe begins to find one half of
the address for the required data. Once the row is located, tRCD
is initiated, cycles out, and then the exact HEX location of the
data required is accessed via CAS. The time between CAS start
and CAS end is the CAS latency. Since CAS is the last stage in
actually finding the proper data, it's the most important step
of memory timing.
Delay between row access and column access
strobe - Important for multi-tasking. (Unknown source)
Also known as RAS to CAS Delay, in addition to Column Address
Strobe, there is Row Address Strobe. CAS and RAS combined allow
for the exact location of memory blocks. There is an interval
between RAS (activated when data is first requested) and CAS
(activated when RAS is complete), as memory can't locate a block
precisely in a single stage. tRCD is the cycle time between the
first stage in memory access, the row strobe, and the second
stage. However, the performance impact of this setting is often
neglible, as memory tries to store data from programs in
sequential order. It tries to keep the same row for a single
program, and ordered columns to reduce the time for tRCD.
Switches active row - Important for memory
copy operations, and apps that use large amounts of memory in
different memory "rows". (Unknown source)
Also known as RAS Precharge, this is the amount of time it takes
for memory to terminate the access in one row and begin another.
To put it simply, after data is set to the pins and activates
tRAS, then RAS, tRCD, and CAS; the memory needs to terminate its
current row and start all over at tRAS. This is the very basic
function of how memory works. This is only an important setting
when you're doing massive shifting in data, for example -
working with large virtual buffers or video rendering. At that
point, several rows are being consumed by a single program, and
its advantageous for the program to be able to switch quickly
between these rows.
Formula for setting tRAS = tCl (CAS latency)
+ tRtc (ras to CAS delay) + 2 (Well-known formula)
Also known as Active to Precharge Delay, this is the time
between receiving a request for data electronically on the pins
of a memory module and then initiating RAS to start the actual
retrieval of data. This command seems important, but really it
isn't. Memory access is a very dynamic thing. Sometimes memory
is being hit hard, and other times very sporadically. Though at
all times, memory access is at constant, therefore, it is rare
that the tRAS command is received to access new data (such as a
substantial change, like opening a new program).
CMD rate is generally used to describe the
time from a chip select until a Row Activate Command can be
given. The chip select defines the physical bank in which the
row is located. In a system running a single, single-sided
memory module, there is never a question which bank will be
selected since there is only one.
More generally, the CMD Rate is a chipset latency that is not
determined by the memory but by the time it takes the chipset to
translate the virtual address space into physical memory
addresses. Needless to say that higher density system memory
with its more addresses will take longer to decode than a single
low density module, even if it is double-sided.
Intel has taken care of this problem by simply limiting the
number of banks supported per memory channel to four. This, in
turn allows them to run all their chipsets on a fixed CMD rate
of 1T, regardless of how much memory is installed.
Rating a module as 1T is actually somewhat misleading
advertising because all unbuffered modules are capable of a 1T
CMD rate up to four banks per channel, beyond which chipset
limitations become a factor.
Formula for setting tRC = tRp (RAS precharge)
+ tRas (precharge delay) (Well-known formula)
Row Cycle Time. The minimum time in cycles it takes a row to
complete a full cycle. If this is set too short it can cause
corruption of data and if it is to high, it will cause a loss in
performance, but increase stability.
Row Refresh Cycle Timing. This determines
the amount of cycles to refresh a row on a memory bank. If this
is set too short it can cause corruption of data and if it is
too high, it will cause a loss in performance, but increased
stability.
Write Recovery Time. The amount of cycles
that are required after a valid write operation and precharge.
This is to insure that data is written properly.
Write to Read Delay. The amount of cycles
required between a valid write command and the next read
command. Lower is better performance, but can cause instability.
Row to Row Delay or RAS to RAS Delay. The
amount of cycles that it takes to activate the next bank of
memory. It is the opposite of tRAS. The lower the timing, the
better the performance, but it can cause instability.
Means for adjusting the timing of each
individual memory phase associated with the selected memory
divider.
a.k.a. "MCH Read Delay" a.k.a. "Common Performance Level" =
means for adjusting the timing of each individual memory phase
associated with the selected memory divider.
Each individual phase can be "pulled-in" or left as is.
"Pulling-in" a phase reduces just that phase's associated tRD
value (performance level) by one. Like memory timings, lower
values are tighter and thus provide better memory read
performance and lower latencies. If all phases are pulled-in,
this is the equivalent of selecting the next lower common
performance level and performs identically to this new setting.
Thus, pulling-in particular phases can allow the user to affect
a minor performance improvement if selecting the next lower
common performance level is not possible.
ClocK; the length of a clock cycle. (Unknown
source)
Write CAS number. Write to whatever bank is open to be written
too. Operates at a rate of 1T, but can be set to others. It does
not seem to work with other settings than 1T on DDR. DDR2 is
different though.
